1. Field of the Invention
The present invention relates to a logic-synthesis method and a logic synthesizer that allows designing a large scale integration (LSI) with efficiency, and particularly relates to a logic-synthesis method and a logic synthesizer that can achieve the target performance of an LSI at an early stage by increasing the quality of a library used for performing logic synthesis.
2. Description of the Related Art
The step of developing a system LSI is usually divided into two steps including the step of performing logic design, that is, register transfer level (RTL) design and the step of performing layout design.
In the past, timing estimation performed by using a wire-load model during the RTL-design phase allows reducing timing violation without making significant correction during the layout-design step, even though the system-LSI development system is divided into the above-described two steps. That is to say, the system-LSI development step could be divided into the RTL-design step and the layout-design step with success. Here, the term “wire-load model” denotes a timing model adapted to estimate a signal delay on the basis of a load connected to a circuit net and the drive ability of a logic circuit.
In recent years, however, the signal delay has become increasingly susceptible to a wiring delay instead of a logic-gate delay that can be estimated by using the wire-load model, as the wiring of semiconductor devices becomes increasing smaller. Since the wiring delay cannot be estimated during the RTL-design phase, unexpected timing violation often occurs. Particularly, when fanout becomes high, that is, when high-fanout connection is generated due to a certain RTL description, the wiring delay that cannot be estimated during the RTL-design phase becomes so significant that serious timing violation occurs. Subsequently, significant correction has to be made during the layout-design step, so as to resolve the serious timing violation.
Although the layout design is corrected, it is not assured that the timing violation will never occur. Therefore, it has been proposed to take measures against the timing violation during the RTL-description phase.
For example, according to a logic-synthesis method disclosed in Japanese Unexamined Patent Application Publication No. 2002-312411, first, RTL analysis is performed, and the position of a description showing high fanout is detected. Next, when the processing proceeds to the step of designing layout, a clock tree whose fanout can be adjusted by adjusting wiring or the like is inserted in the high-fanout description of the RTL description.
Subsequently, it becomes possible to improve timing without making a significant layout change when the layout is designed after the logic synthesis is performed. Further, it becomes possible to design the most suitable layout and wiring, and achieve appropriate load balancing.
Further, the LSI performance, that is, the relationship between consumption power and speeding up timing should be calculated during the RTL-design phase. However, since the logic-synthesis method disclosed in Japanese Unexamined Patent Application Publication No. 2002-312411 does not allow performing appropriate layout and wiring, load balancing is not achieved. Therefore, when the LSI performance is determined by a circuit path including a high-fanout position, the processing proceeds to the layout-design step irrespective of the LSI performance. Subsequently, the deterioration of timing, increased consumption power, and so forth that are caused by an improvement in consumption power or the like that is made during the layout-design step cannot be estimated.